XJTAG XJLink-PF20, the latest addition to the XJLink-PF series, brings dependability and robustness to a new 4-TAP two-port configuration, offering both functional and JTAG boundary scan testing.

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

It is now possible to create a single baseline project and then to define how each variant differs from that baseline. Importing BOM files for each variant allows you to use a wizard that compares the ...

The Boundary-scan, aka JTAG (Joint Test Action Group), is the IEEE 1149.1 standard used to verify and test Integrated Circuits (IC) interconnections on the PCBs. Using the boundary scan in PCB ...

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area ...

Corelis announced version 9.4 of its ScanExpress Boundary-Scan Suite of Software is now available. ScanExpress Runner now includes an asynchronous API for integration with third party applications.

Following requests from customers, XJTAG has introduced an API that allows engineers to use XJAnalyser’s ability to manipulate the pins of JTAG-enabled ICs in their own software with almost no set up.

A new NASA mission, the first to hitch a ride on a commercial communications satellite, will examine Earth's upper atmosphere to see how the boundary between Earth and space changes over time.

ScanExpress Version 8.4 allows dynamic driving and sensing of GPIO signals on Corelis USB-1149.1/1E and USB-1149.1/4 JTAG controllers using the main ScanExpress Debugger graphical interface. The ...

At Alcatel-Lucent, we test chassis-level products that provide 42 board slots on a midplane, essentially a passive backplane that accepts boards on its front and rear sides. Thirty-four of those slots ...