I'm pretty sure the Xilinx ISE Webpacks are available free to use. They are limited to the size of devices you can generate bitstreams for. Not sure on the simulation limitations. I'm not sure of ...

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...

Internal benchmarks for designs running in "single step clock mode" (hardware in lockstep with software simulation) have resulted in performance improvements from 7X to 112X times faster than ...

SDAccel automates the acceleration of software application written in C, C++ or OpenCL by building application-specific FPGA kernels for Amazon EC2 F1. SDAccel also supports traditional hardware ...

These are typically used for compute-intensive workloads like data analytics, video processing and machine learning. SDAccel, which is accessible through the AWS FPGA developer AMI, also supports ...

Aldec's OEM simulator will be the default VHDL or Verilog FPGA simulation technology in the next release of Altium Designer, currently scheduled for release in the next few weeks.

According to Aldec (Henderson, Nev.), Active-HDL 8.2 sp1 includes full support for Xilinx SecureIP, IEEE VHDL/Verilog-encrypted IP and an enhanced assertions bundle option.