MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...

UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, ...

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...

With the increasing adoption of OVM/UVM, there is a growing demand for guidelines and best practices to ensure successful SoC verification. It is true that the verification problems did not change but ...

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...

The 90-minute tutorial focuses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them ...