Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not ...

Recently, many methodologies have been introduced for reducing dynamic power for systems-on-chip (SoCs). These methodologies, however, impose restrictive physical constraints which have schedule ...

As FPGA device sizes have expanded over the last few years to exceed the one million gate mark, design methodologies have changed also. Design approaches, such as using latches and asynchronous ...

The MC1030 is a clocked dual D-type latch. Any change in the D input will be reflected at the output while the clock is low. The outputs are latched on the clock's ...

With prior knowledge of delay characterization for combinational standard cells, where the delay values are dependent on the input slew and the output load, one needs to take in account of the ...

A couple years back we covered a very impressive transistor logic clock which was laid out so an observer could watch all of the counters doing their thing, complete with gratuitous blinkenlights. It ...